K9WAG08U1M Datasheet, PDF (45/49 Pages) Samsung semiconductor – 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory

K9WAG08U1M
K9K8G08U0M
Preliminary
FLASH MEMORY
Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input
tR
tR
R/B
I/Ox
00h Add.(5Cycles) 35h
00h Add.(5Cycles) 35h
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2 & Row Add.1,2,3
Source Address On Plane0
Source Address On Plane1
1
R/B
I/Ox
R/B
I/Ox
tDBSY
85h
Add.(5Cycles)
Data
85h
Add.(2Cycles)
Data
11h
1
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2
Note4
2
Destination Address
A0 ~ A11 : Valid
A12 ~ A17 : Fixed ’Low’
A18
: Fixed ’Low’
A19 ~ A29 : Fixed ’Low’
A30
: Valid
tPROG
81h
Add.(5Cycles)
Data
85h
Add.(2Cycles)
Data
10h
Col. Add.1,2 & Row Add.1,2,3
2
Destination Address
Col. Add.1,2
A0 ~ A11 : Valid
A12 ~ A17 : Valid
A18
: Fixed ’High’
A19 ~ A29 : Valid
A30
: Must be same as previous A30
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd address page(target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
3. EDC status Bits are not available during copy back for some bits or bytes modified by Random Data Input operation.
In case of the 528 byte plane unit modification, EDC status bits are available.
4. Any command between 11h and 81h is prohibited except 70h and FFh.
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