S5T8610 Datasheet, PDF (4/27 Pages) Samsung semiconductor – DIGITAL CLP MODEM WITH ADPCM CODEC

S5T8610
PRELIMINARY
DIGITAL CLP MODEM WITH ADPCM CODEC
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Symbol
VREF
AGND
VDDA_ADC
VSSA_ADC
RXI
VRT
VRB
TXO
VDDA_DAC
VSSA_DAC
VDDD_DAC
VSSD_DAC
VDDD1
TCLKDR
TSHFTDR
TUPDDR
TSELDR0
TSELDR1
TIDR
TODR
TINT
CKOUT
VDDD_OSC
OSCI
OSCO
VSSD_OSC
TEST0
TEST1
TEST2
TEST3
SYNCH/BER/JAM
VSSD1
I/O
Description
AI Reference top (3.3V) for ADC
AI Reference bottom (0V) for ADC
AP Analog power (3.3V) for ADC
AG Analog ground (0V) for ADC
AI Analog input (input range: 0V to 3.3V) for ADC
AI Voltage reference top (2.0V) for DAC
AI Voltage reference bottom (0V) for DAC
AO Analog voltage output for DAC
AP Analog power (3.3V) for DAC
AG Analog ground (0V) for DAC
DP Digital power (3.3V) for DAC
DG Digital ground (0V) for DAC
DP Digital power (3.3V) for DSP core
DI Test clock
DI Test scan shift enable
DI Test scan update
DI Test scan register selection 0
DI Test scan register selection 1
DI Test scan input
DO Test scan output
DO Interrupt check
DO Test clock output
DP Digital power (3.3V) for oscillator block
I
Oscillator input
O Oscillator output
DG Digital ground (0V) for oscillator block
DI Test
DI Test
DI Test
DI Test
DO Initial synchronization / BER (bit error rate) / jamming
detection output
DG Digital ground (0V)
4