S5T8610 Datasheet, PDF (10/27 Pages) Samsung semiconductor – DIGITAL CLP MODEM WITH ADPCM CODEC

S5T8610
PRELIMINARY
DIGITAL CLP MODEM WITH ADPCM CODEC
Host Interface Unit
S5T8610 receives commands and parameters in serial format, starting from the MSB, from the host through the
host interface unit (HIU). The data is in byte units. The HIU has HWEB (Host Write Enable), HCLK (Host
Interface Clock), and HDATA (Host Data) pins. The maximum HBCK frequency is 4MHz. S5T8610 can accept
the host command every 20µsec.
Characteristic
Clock Frequency (1/Tck)
Clock Pulse Width
Setup Time
Hold Time
Symbol
Fck
Twck
Ts
Th
MIN
TYP
MAX
Unit
−
−
1.67
MHz
750
−
−
ns
300
−
−
ns
300
−
−
ns
HCLK
HDATA
HWEB
Tck=1/Fck
Twck Twck
MSB
Ts Th
LSB
System Clock
S5T8610 operates only with 36.8 MHz or 36.864 MHz external clock.
Reset
S5T8610 provides power-on-reset circuit and RESET pin for external hardware reset. For power-on-reset, the
RESET signal is held normally low. For the external hardware reset, the device is in the reset state when the host
sets RESET signal to high. The device is in the operating state, when the host inputs low to the RESET pin.
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