K7S1636U4C Datasheet, PDF (4/20 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 QDR II+ b4 SRAM

K7S1636U4C
K7S1618U4C
512Kx36 & 1Mx18 QDR^TM II+ b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7S1636T4C (512Kx36)
1
2
3
4
5
6
7
8
9
10
11
A
CQ NC/SA* NC/SA*
W
BW2
K
BW1
R
NC/SA* NC/SA* CQ
B
Q27
Q18
D18
SA
BW3
K
BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
NC
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
QVLD
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 9A for 36Mb, 3A for 72Mb, 10A for 144Mb and 2A for 288Mb.
2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35.
PIN NAME
SYMBOL
K, K
QVLD
CQ, CQ
Doff
SA
D0-35
PIN NUMBERS
6B, 6A
6P
11A, 1A
1H
4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
DESCRIPTION
Input Clock
Q Valid output
Output Echo Clock
DLL Disable
Address Inputs
Data Inputs
NOTE
Q0-35
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
Data Outputs
W
4A
Write Control Pin,active when low
R
8A
Read Control Pin,active when low
BW0, BW1,BW2, BW3
7B,7A,5A,5B
Block Write Control Pin,active when low
VREF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input 1
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V )
VSS
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,8M,4N,8N
Ground
TMS
TDI
TCK
TDO
NC
10R
11R
2R
1R
2A,3A,10A,6C,6R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
2
Notes:
1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
2. Not connected to chip pad internally.
3. K, K can not be set to VREF voltage.
Rev. 1.0 August 2008
-4-