K7S1636U4C Datasheet, PDF (15/20 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 QDR II+ b4 SRAM

K7S1636U4C
K7S1618U4C
512Kx36 & 1Mx18 QDR^TM II+ b4 SRAM
TIMING WAVE FORMS OF READ AND NOP
READ
tKHK
tKLKH
K
READ
tKHKL
tKHKH
K
tAVKH tKHAX
NOP
NOP
SA A1
tIVKH tKHIX
R
QVLD
Q
(Data Out)
CQ
A2
tQVLD
tKHQV
tKHQX
tQVLD
Q1-1 Q1-2 Q1-3
tKHCQV
tKHCQX
tCQHQV
Q1-4
Q2-1
Q2-2 Q2-3
tCQHQX
Q2-4
CQ
Don′t Care Undefined
Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
TIMING WAVE FORMS OF WRITE AND NOP
WRITE
tKHKH
tKLKH
K
WRITE
tKHKL
tKHKH
K
tAVKH tKHAX
SA
A1
tIVKH tKHIX
W
A2
tKHIX
NOP
NOP
D(Data In)
D1-1 D1-2 D1-3 D1-4 D2-1 D2-2 D2-3 D2-4
tDVKH
tKHDX
Don′t Care
Note: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+0.
2. BWx assumed active.
Undefined
Rev. 1.0 August 2008
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