K7R643682M Datasheet, PDF (4/19 Pages) Samsung semiconductor – 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM

K7R643682M
K7R641882M
K7R640982M
Preliminary
2Mx36 & 4Mx18 & 8Mx9 QDR^TM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R641882M(4Mx18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/SA*
SA
W
BW1
K
NC
R
SA
SA
CQ
B
NC
Q9
D9
SA
NC
K
BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
SA
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-17
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
NOTE
1
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
Data Outputs
W
R
BW0, BW1
VREF
ZQ
VDD
VDDQ
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Write Control Pin,active when low
Read Control Pin,active when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input 2
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
VSS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
TDI
TCK
TDO
NC
10R
11R
2R
1R
7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
Oct. 2004
Rev 0.5