K4H560438E-NC Datasheet, PDF (4/24 Pages) Samsung semiconductor – 256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)

DDR SDRAM 256Mb E-die (x4, x8)
Pin Description
DDR SDRAM
54pin sTSOP(II)-300
VDD
VDD
1
DQ0
NC
2
VDDQ VDDQ
3
DQ1
DQ0
4
VSSQ
VSSQ
5
DQ2
NC
6
VDDQ VDDQ
7
DQ3
DQ1
8
VSSQ
VSSQ
9
NC
NC
10
VDDQ VDDQ
11
NC
NC
12
NC
NC
13
VDD
VDD
14
WE
WE
15
CAS
CAS
16
RAS
RAS
17
CS
CS
18
NC
NC
19
BA0
BA0
20
BA1
BA1
21
AP/A10 AP/A10
22
A0
A0
23
A1
A1
24
A2
A2
25
A3
A3
26
VDD
VDD
27
32Mb x 8
64Mb x 4
54
53
52
51
50
49
48
47
54 PinsTSOP(II)
46
300mil x 551mil
45
(7.62mm x 14.00mm)
44
43
(0.5 mm Pin Pitch)
42
Bank Address
41
BA0-BA1
40
39
Row Address
38
A0-A12
37
36
Auto Precharge
35
A10
34
33
32
31
30
29
28
VSS
NC
VSSQ
DQ3
VDDQ
NC
VSSQ
DQ2
VDDQ
NC
VSSQ
DQS
VREF
VSS
DM
CK
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
VSSQ
DQS
VREF
VSS
DM
CK
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Organization
64Mx4
32Mx8
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.3 April, 2005