K4H511638C-Z Datasheet, PDF (4/24 Pages) Samsung semiconductor – 512Mb C-die DDR SDRAM Specification

DDR SDRAM 512Mb C-die (x4, x8, x16)
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA Pb-Free package
• RoHS compliant
DDR SDRAM
2.0 Ordering Information
Part No.
K4H510438C-ZC/LCC
K4H510438C-ZC/LB3
K4H510838C-ZC/LCC
K4H510838C-ZC/LB3
K4H511638C-ZC/LCC
K4H511638C-ZC/LB3
Org.
128M x 4
64M x 8
32M x 16
Max Freq.
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Interface
SSTL2
SSTL2
SSTL2
Package
60ball FBGA
60ball FBGA
60ball FBGA
3.0 Operating Frequencies
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
CC(DDR400@CL=3)
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
Rev. 1.1 June. 2005