K4H510838B-N Datasheet, PDF (4/24 Pages) Samsung semiconductor – 512Mb B-die DDR SDRAM Specification 54 sTSOP-II (400mil x 441mil)

DDR SDRAM 512Mb B-die (x8)
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 54pin sTSOP(II)-400 (Leaded & Pb-Free(RoHS compliant)) package
DDR SDRAM
2.0 Ordering Information
Part No.
Org.
Max Freq.
Interface
Package
K4H510838B-N(V)C/LCC
CC(DDR400@CL=3)
K4H510838B-N(V)C/LB3
K4H510838B-N(V)C/LA2
64M x 8
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
SSTL2
54pin sTSOP II
K4H510838B-N(V)C/LB0
B0(DDR266@CL=2.5)
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (N : 54 sTSOP with Leaded, V : 54 sTSOP with Lead-free)
3.0 Operating Frequencies
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
CC(DDR400@CL=3)
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2.0)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
Rev. 1.3 June. 2005