K9F5608Q0C Datasheet, PDF (38/42 Pages) Samsung semiconductor – 32M x 8 Bit , 16M x 16 Bit NAND Flash Memory

K9F5608Q0C K9F5616Q0C
K9F5608D0C K9F5616D0C
K9F5608U0C K9F5616U0C
FLASH MEMORY
2. Block Lock Status Read
Block Lock Status can be read on a block basis, which may be read to find out whether designated block is available to be pro-
grammed or erased. After writing 7Ah command to the command register. and block address to be checked, a read cycle outputs the
content of the Block Lock Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control
allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or
CE does not need to be toggled for updated status. Blcok Lock Status Read is prohibited while the device is busy state.
Refer to table 6 for specific Status Register definitions. The command register remains in Block Lock Status Read mode until further
commands are issued to it. In high state of LOCKPRE pin, write protection status can be checked by Block Lock Status
Read(7Ah) while in low state by Status Read(70h).
(1)Lock
(2)unlock
(1)Lock
Read 1) block
case
Read 2) block
case
Read 3) block
case
Read 4) block
case
(3)Lock-tight
(4)unlock
(3)Lock-tight
IO7~IO3
X
IO2(Unlock)
0
IO1(Lock)
1
IO0(Lock-tight)
0
X
1
1
0
X
0
0
1
X
1
0
1
(1)Lock
(2)Unlock
(3)Lock-tight
Table6. Block Lock Status Register definitions
WP
CLE
CE
WE
ALE
RE
I/Ox
tWHR2
7Ah
Read Block Lock
status Command
Add.1 Add.2
Block Address 2cycle
Dout
Block Lock Status
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