K9L8G08U1A Datasheet, PDF (36/44 Pages) Samsung semiconductor – 512M x 8 Bit / 1G x 8 Bit NAND Flash Memory

K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Preliminary
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A19 to A29 is valid while A12 to A18 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 10 details the sequence.
Figure 10. Block Erase Operation
tBERS
R/B
I/Ox
60h
Address Input(3Cycle)
D0h
"0"
70h
I/O0
Pass
Row Add. : A12 ~ A29
"1"
Fail
Two-Plane Read
Two-Plane Read is an extension of Read, for a single plane with 2,112 byte page registers. Since the device is equipped with two
memory planes, activating the two sets of 2,112 byte page registers enables a random read of two pages. Two-Plane Read is initi-
ated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can be selected
from each plane.
After Read Confirm command(30h) the 4,224 bytes of data within the selected two page are transferred to the data registers in less
than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five
Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the
identical command sequences. The restrictions in addressing with Two-Plane Read are shown in Figure 11. Two-Plane Read must
be used in the block which has been programmed with Two-Plane Page Program.
Figure 11. Two-Plane Page Read Operation with Two-Plane Random Data Out
R/B
tR
I/OX 60h
Address (3 Cycle)
60h
Address (3 Cycle)
30h
Row Add.1,2,3
Row Add.1,2,3
A12 ~ A18 : Fixed ’Low’
A12 ~ A18 : Valid
A19
: Fixed ’Low’
A19
: Fixed ’High’
1
A20 ~ A29 : Fixed ’Low’
A20 ~ A29 : Valid
R/B
I/Ox
00h
Address (5 Cycle)
05h
Address (2 Cycle)
E0h
Data Output
Col. Add. 1,2 & Row Add.1,2,3
Col. Add.1,2
1
A0 ~ A11 : Fixed ’Low’
A0 ~ A11 : Valid
2
A12 ~ A18 : Fixed ’Low’
A19
: Fixed ’Low’
A20 ~ A29 : Fixed ’Low’
R/B
I/Ox
00h
Address (5 Cycle)
05h
Address (2 Cycle)
E0h
Col. Add. 1,2 & Row Add.1,2,3
Col. Add.1,2
2
A0 ~ A11 : Fixed ’Low’
A0 ~ A11 : Valid
A12 ~ A18 : Fixed ’Low’
A19
: Fixed ’High’
A20 ~ A29 : Fixed ’Low’
Data Output
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