K9E2G08U0M Datasheet, PDF (36/38 Pages) Samsung semiconductor – 256M x 8 Bits NAND Flash Memory

K9E2G08U0M
Figure 21-2. Read ID (2) Operation
CLE
CE
WE
ALE
RE
I/O0~7
tCEA
tAR
tWHR
91h
00h
Address. 1cycle
tREA
20h
Extended ID Code
Preliminary
FLASH MEMORY
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 22 below.
Figure 22. RESET Operation
tRST
R/B
I/O0~7
FFh
Table5. Device Status
Operation Mode
After Power-up
Read 1
After Reset
Waiting for next command
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