S3C852B Datasheet, PDF (308/383 Pages) Samsung semiconductor – 8-BIT CMOS MICROCONTROLLERS

CALLER ID BLCOK
S3C852B/P852B (Preliminary Spec)
FSK DATA RECEPTION
FSK Data Reception Sequence
The on-chip FSK receiver satisfies all target specifications of Bellcore. The FSK receiver function can be enabled
by setting the FSKenable bit (Function register, bit2) and clearing the CASenable (Function register, bit1) and the
SDTenable (Function register, bit5) bits.
When the FSK receiver is enabled, the CID BLOCK continuously checks for a signal in the FSK band (~1200 -
~2200 Hz) above the minimum signal level threshold. An FSK data word consists of one start bit (space) followed
by eight data bits and one stop bit (mark). After the FSK receiver has detected a start bit it starts receiving the
data bits (LSB first). After the 8^th data bit the FSKint interrupt bit (Interrupt register, bit2) is set and an interrupt is
generated.
The FSKint interrupt bit is cleared when the Interrupt register is read. The interrupt register and the FSKDT
register should be read every time an interrupt occurs.
FSK data
FSKint
INT
D0 D1 D2 D3 D4 D5 D6 D7
Interrupt register is read.
Figure 14-5. Sequence to Receive an FSK Data Byte
The parameters of the FSK receiver are shown in Table 14-2.
Table 14-2. FSK Receiver Parameters
Parameter
Mark frequency (logic 1)
Space frequency (logic 0)
Maximum allowed signal level
Minimum signal level threshold
Twist
Accepted S/N (0Hz – 200Hz)
Accepted S/N (200Hz – 3200Hz)
Accepted S/N (3200Hz – 15000Hz)
Transmission rate
Bellcore
1200Hz ± 1%
2200Hz ± 1%
0dBm
<-45dBm
-10dB to +10dB
<-20dB
<6dB
<-20dB
1200 bits per second 1%
CCITT/ V23
1300Hz ± 1.5%
2100Hz ± 1.5%
-8dBV
<-52dBV
-6dB to +6dB
<-20dB
<6dB
<-20dB
1200 bits per second 1%
14-6