S3C852B Datasheet, PDF (128/383 Pages) Samsung semiconductor – 8-BIT CMOS MICROCONTROLLERS

INTERRUPT STRUCTURE
S3C852B/P852B (Preliminary Spec)
SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing. Figure 5-5 shows the effect of the various control settings.
A reset clears SYM.7, SYM.1, and SYM.0 to "0" and the other SYM bit values (for fast interrupt level selection)
are undetermined.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which
follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to
enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this
purpose.
MSB .7
System Mode Register (SYM)
DEH, Set 1, R/W
.6 .5 .4 .3 .2 .1
.0 LSB
Not used
External interface tri-state
enable bit:
0 = Normal operation
(Tri-state disable)
0 = High inpedence
(Tri-state enable)
Global interrupt enable bit:
0 = Disable all interrupts
1 = Enable all interrupts
Fast interrupt level
selection bits:
Fast interrupt enable bit:
0 0 0 IRQ0
0 0 1 IRQ1
0 = Disable fast interrupts
1 = Enable fast interrupts
0 1 0 IRQ2
0 1 1 IRQ3
1 0 0 IRQ4
1 0 1 Not used for S3C852B/P852B
1 1 0 IRQ6
1 1 1 IRQ7
Figure 5-5. System Mode Register (SYM)
5-8