DDRSDRAM Datasheet, PDF (30/49 Pages) Samsung semiconductor – DDR SDRAM Specification Version 0.61

128Mb DDR SDRAM
Target
3.3.12 Write with Auto Precharge
If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new
command to the same bank should not be issued until the internal precharge is completed. The internal pre-
charge begins after keeping tWR(min).
< Burst Length=4 >
0
CK
CK
Command
BANK A
ACTIVE
1
2
3
NOP
WRITE A
Auto Precharge
NOP
DQS
4
NOP
5
NOP
6
NOP
DQ ′s
Din 0 Din 1 Din 2 Din 3
tWR
7
8
NOP
NOP
* Bank can be reactivated at
completion of tRP
tRP
Internal precharge start
Figure 20. Write with auto precharge timing
Burst length = 4
Asserted
command
WRITE
3
WRITE+
No AP^*1
4
WRITE+
No AP
For same Bank
5
6
WRITE+
No AP
Illegal
For Different Bank
7
8
3
4
5
6
7
Illegal Illegal Legal Legal Legal Legal Legal
WRITE+
AP
WRITE+ WRITE+
AP
AP
WRITE+
AP
Illegal
Illegal Illegal Legal Legal Legal Legal Legal
READ
Illegal
READ+NO _READ+NO
AP+DM^*2
AP+DM
READ+
NO AP
READ+
NO AP
Illegal Illegal Illegal
Legal Legal Legal
READ+AP Illegal
READ +
AP+DM
READ +
AP+DM
READ +
AP
READ +
AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Illegal Illegal Illegal Legal Legal Legal
Precharge Illegal
Illegal
Illegal
Illegal Illegal Illegal Legal Legal Legal
*1 _{: AP = Auto Precharge}
*2 _{: DM : Refer to " 3.3.7 Write Interrupted by a Read & DM " in page 25.}
Table 7. Operating description when new command asserted
while write with auto precharge is issued
Legal
Legal
Legal
Legal
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REV. 0.61 August 9. '99