K9F4008W0A- Datasheet, PDF (3/24 Pages) Samsung semiconductor – 512K x 8 bit NAND Flash Memory

K9F4008W0A-TCB0, K9F4008W0A-TIB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
FLASH MEMORY
A7 - A18
A0 - A6
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
Command
Register
4M Bit
NAND Flash ARRAY
32Byte x 4Frames x 4096Rows
Page Register & S/A
Y-Gating
I/O Buffers & Latches
CE
Control Logic
RE
& High Voltage
WE
Generator
I/O0
Global Buffers
I/O7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
4K Rows
(=128 Blocks)
The 1st Block (4KB)
1
2
3
4
128Bytes
Frame Register
32 Bytes
Good Block
1Block = 32 Rows
= 4K Bytes
1 Frame = 32 Bytes
1 Row = 4 Frames = 128 Bytes
1 Block = 32 Rows = 4K Bytes
1 Device = 32Bytes x 4Frames x 32Rows x 128Blocks
= 4Mbits
8 bit
I/O0 ~ I/O7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A8
A9
A10
A11
A12
A13
A14
3rd Cycle A16
A17
A18
X*⁽¹⁾
X*
X*
*X
NOTE : *(1) : X can be VIL or VIH
* The device ignores any additional input of address cycles than reguired.
I/O7 _{Column Address (A0-A4)}
A7 ^{Frame Address (A5-A6)}
A15 ^{Row Address (A7-A11)}
Block Address (A12-A18)
*X
3