K9F4008W0A- Datasheet, PDF (17/24 Pages) Samsung semiconductor – 512K x 8 bit NAND Flash Memory

K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
DEVICE OPERATION
FRAME READ
Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also ini-
tiated by writing 00h to the command register along with three address cycles. The three cycle address input must be given for
access to each new frame.
The read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the data
registers in less than 15µs(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once
the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing RE with CE staying
low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address
within the frame(column 32).
Figure 3. Read Operation
CLE
CE
WE
ALE
RE
R/B
I/O0~7
Busy(Seek Time)
00h ^{Start Add.(3Cycle)}
A0~A7 & A8~A18
Seek Time
0
31
Data Output(Sequential)
17