K7A321800M Datasheet, PDF (3/18 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 Synchronous SRAM

K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
•Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
•On-Chip Address Counter.
•Self-Timed Write Cycle.
•On-Chip Address and Control Registers.
•VDD= 3.3V +0.165V/-0.165V Power Supply.
•I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
•5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
•Power Down State via ZZ Signal.
•LBO Pin allows a choice of either a interleaved burst or a linear
burst.
•Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
•Asynchronous Output Enable Control.
•ADSP, ADSC, ADV Burst Control Pins.
•TTL-Level Three-State Output.
• 100-TQFP-1420A Package
•Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Symbol -25
-20
-14
Unit
Cycle Time
tCYC
4.0
5.0
7.2
ns
Clock Access Time
tCD
2.6
3.1
4.0
ns
Output Enable Access Time tOE
2.6
3.1
4.0
ns
GENERAL DESCRIPTION
The K7A323600M and K7A321800M are 37,748,736-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
It is organized as 1M(2M) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; G W, BW , LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by G W, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache control-
ler( ADSC) inputs. Subsequent burst addresses are gener-
ated internally in the system′s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst
sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A323600M and K7A321800M are fabricated using
SAMSUNG′s high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS _{A′0~A′1}
COUNTER
1Mx36 , 2Mx18
MEMORY
ARRAY
ADSP
A0~A19
or A0~A20
A0~A1
ADDRESS
REGISTER
A2~A19
or A2~A20
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~DQd7 or DQa0 ~ DQb7
DQPa ~ DQPd DQPa,DQPb
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DATA-IN
REGISTER
-3-
Nov. 2003
Rev 2.0