K4S161622H Datasheet, PDF (3/11 Pages) Samsung semiconductor – 16Mb H-die SDRAM Specification

SDRAM 16Mb H-die(x16)
512K x 16Bit x 2 Banks SDRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• two banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 32ms refresh period (2K cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S161622H is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated
with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/
O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten-
cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part NO.
K4S161622H-TC55
K4S161622H-TC60
K4S161622H-TC70
K4S161622H-TC80
MAX Freq.
183MHz
166MHz
143MHz
125MHz
Interface
LVTTL
Package
50pin
TSOP(II)
Organization
1Mx16
Row Address
A0~A10
Column Address
A0-A7
Row & Column address configuration
Rev. 1.5 August 2004