K4S161622H Datasheet, PDF (10/11 Pages) Samsung semiconductor – 16Mb H-die SDRAM Specification

SDRAM 16Mb H-die(x16)
CMOS SDRAM
(AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CAS Latency=3
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
CAS Latency=2
Output data
CLK high pulse
width
CAS Latency=3
CAS Latency=2
CLK low pulse
width
CAS Latency=3
CAS Latency=2
Input setup time
CAS Latency=3
CAS Latency=2
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS Latency=3
CAS Latency=2
Symbol
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
55
Min Max
5.5
1000
10
-
5
-
6
2
-
2
-
3
2
-
3
1.5
-
2
1
-
1
-
-
5
-
6
60
Min Max
6
1000
10
-
5.5
-
6
2.5
-
2.5
-
3
2.5
-
3
1.5
-
2
1
-
1
-
-
5.5
-
6
-70
Min Max
7
1000
10
-
5.5
-
6
2.5
-
3
-
3
-
1.75
-
2
1
-
1
-
-
5.5
-
6
-80
Min Max
8
1000
10
-
6
-
6
2.5
-
Unit
ns
ns
ns
Note
5
5, 6
6
3
-
ns
7
3
-
ns
7
2
-
ns
7
1
-
ns
7
1
-
ns
6
-
6
ns
-
6
Notes : _{1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then}
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Parameters depend on programmed CAS latency.
6. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
7. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
8. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 1.5 August 2004