K4H56038D-TC Datasheet, PDF (3/18 Pages) Samsung semiconductor – 256Mb D-die DDR400 SDRAM Specification

DDR SDRAM 256Mb D-die (x8, x16)
Key Features
• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
DDR SDRAM
Ordering Information
Part No.
K4H560838D-TCCC
K4H560838D-TCC4
K4H561638D-TCCC
K4H561638D-TCC4
Org.
32M x 8
16M x 16
Max Freq.
CC(DDR400@CL=3)
C4(DDR400@CL=3)
CC(DDR400@CL=3)
C4(DDR400@CL=3)
Operating Frequencies
Speed @CL3
CL-tRCD-tRP
- CC(DDR400@CL=3)
200MHz
3-3-3
*CL : CAS Latency
- C4(DDR400@CL=3)
200MHz
3-4-4
Interface
SSTL2
SSTL2
Package
66pin TSOP II
66pin TSOP II
Rev. 1.1 Feb. 2003