K4H56038D-TC Datasheet, PDF (11/18 Pages) Samsung semiconductor – 256Mb D-die DDR400 SDRAM Specification

DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM I_DD spec table
DDR SDRAM
(V_DD=2.7V, T = 10°C)
Symbol
32Mx8
16Mx16
Unit Notes
- CC(DDR400@CL=3) - C4(DDR400@CL=3) - CC(DDR400@CL=3) - C4(DDR400@CL=3)
IDD0
105
100
110
105
mA
IDD1
130
130
150
145
mA
IDD2P
4
4
4
4
mA
IDD2F
30
30
30
30
mA
IDD2Q
25
25
25
25
mA
IDD3P
55
55
55
55
mA
IDD3N
75
75
75
75
mA
IDD4R
185
185
220
220
mA
IDD4W
220
220
250
250
mA
IDD5
200
200
200
200
mA
IDD6 Normal
3
3
3
3
mA
Low power
1.5
1.5
1.5
1.5
mA Optional
IDD7A
350
350
380
380
mA
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 1.1 Feb. 2003