DS_K7N803601B Datasheet, PDF (3/18 Pages) Samsung semiconductor – 256Kx36 & 512Kx18-Bit Pipelined NtRAM

K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAM^TM
256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined NtRAM^TM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• Α interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A
• Operating in commercial and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -16 -13 Unit
tCYC 6.0 7.5 ns
tCD
3.5 4.2 ns
tOE
3.5 3.8 ns
GENERAL DESCRIPTION
The K7N803601B and K7N801801B are
9,437,184 bits Synchronous Static SRAMs.
The NtRAM^TM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803601B and K7N801801B are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP and Multiple power and ground pins mini-
mize ground bounce.
LOGIC BLOCK DIAGRAM
A [0:17] or
A [0:18]
LBO
A0~A1
ADDRESS
REGISTER A2~A17 or A2~A18
BURST
ADDRESS
COUNTER
A′0~A′1
256Kx36 , 512Kx18
MEMORY
ARRAY
CLK
K
CKE
CS1
CS2
CS2
ADV
WE
BWx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
DATA-IN
K REGISTER
DATA-IN
K _REGISTER
CONTROL
LOGIC
36 or 18
K OUTPUT
REGISTER
BUFFER
NtRAM^TM and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
-3-
Nov. 2003
Rev 3.0