S3P830A Datasheet, PDF (251/342 Pages) Samsung semiconductor – 8-Bit CMOS Microcontroller

BASIC TIMER and TIMER 0
S3C830A/P830A
T0CON is located in set 1, bank 0, at address E2H, and is read/write addressable using Register addressing
mode.
A reset clears T0CON to “00H”. This sets timer 0 to normal interval timer mode, selects an input clock frequency
of fxx/1024, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal
operation by writing a "1" to T0CON.2.
The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address E2H. When a timer 0
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware
or must be cleared by software.
To enable the timer 0 match/capture interrupt (IRQ0, vector E0H), you must write T0CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.1. When a "1" is detected, a
timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit,
INTPND.1.
MSB .7
Timer 0 Control Register (T0CON)
E2H, Set 1, Bank 0, R/W
.6 .5 .4 .3 .2 .1
.0 LSB
Timer 0 input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
011 = fxx/8
100 = fxx
Timer 0 match/capture interrupt enable bit:
101 = External clock
0 = Disable interrupt
(P0.1/T0CLK) falling edge
1 = Enable interrupt
110 = External clock
(P0.1/T0CLK) rising edge
111 = Counter stop
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Timer 0 operating mode selection bits:
00 = Interval mode (P0.3/T0OUT)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF and match
interrupt can occur)
Figure 10-3. Timer 0 Control Register (T0CON)
10-6