S3P830A Datasheet, PDF (101/342 Pages) Samsung semiconductor – 8-Bit CMOS Microcontroller

CONTROL REGISTERS
S3C830A/P830A
PLLMOD — PLL Mode Register
F8H
Set 1, Bank 0
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7
.6
.5
.4
(note)
(note)
(note)
–
R/W
R/W
R/W
–
Register addressing mode only
.3
.2
.1
.0
0
0
0
0
R/W
R/W
R/W
R/W
.7
PLL Frequency Division Method Selection Flag
0 Direct method for AM
1 Pulse swallow method for FM
.6
PLL Enable/Disable Bit
0 Disable PLL
1 Enable PLL
.5
Bit Value to be Loaded into Swallow Counter
NF bit is loaded into the LSB of swallow counter
.4
Not used for the S3C830A
.3
INTIF Interrupt Enable Bit
0 Disable INTIF interrupt
1 Enable INTIF interrupt
.2
INTIF Interrupt Pending Bit
0 Interrupt is not pending (when read)
0 Clear pending bit (when write)
1 Interrupt is pending (when read)
.1
INTCE Interrupt Enable Bit
0 Disable INTCE interrupt requests at the CE pin
1 Enable INTCE interrupt requests at the CE pin
.0
INTCE Interrupt Pending Bit
0 Interrupt is not pending (when read)
0 Clear pending bit (when write)
1 Interrupt is pending (when read)
NOTE: If a system reset occurs during operation mode, the current value contained is retained. If a system reset occurs
after power-on, the value is undefined.
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