S3C24A0 Datasheet, PDF (224/487 Pages) Samsung semiconductor – APPLICATION PROCESSOR FOR 2.5G/3G MOBILE PHONES

BSW rv0.1-0417-N01
S3C24A0 RISC MICROPROCESSOR
IIS-BUS INTERFACE
IIS PRESCALER REGISTER (IISPSR)
Register
Address
IISPSR 0x44700008
R/W
Description
R/W IIS prescaler register
Reset Value
0x0
IISPSR
Prescaler control A
Prescaler control B
Bit
Description
[9:5] Data value : 0 ~ 31
NOTE : Prescaler A makes the master clock that is used
the internal block and division factor is N+1.
[4:0] Data value : 0 ~ 31
NOTE : Prescaler B makes the master clock that is used
the external block and division factor is N+1.
Initial State
00000
00000
IIS FIFO CONTROL REGISTER (IISFCON)
Register
IISFCON
Address
0x4470000C
R/W
Description
R/W
IIS FIFO interface register
Reset Value
0x0
IISFCON
Transmit FIFO access mode select
Receive FIFO access mode select
Transmit FIFO
Receive FIFO
Transmit FIFO data count
(Read only)
Receive FIFO data count
(Read only)
Bit
[15]
[14]
[13]
[12]
[11:6]
Description
0 = Normal
1 = DMA
0 = Normal
1 = DMA
0 = Disable 1 = Enable
0 = Disable 1 = Enable
Data count value = 0 ~ 32
[5:0] Data count value = 0 ~ 32
Initial State
0
0
0
0
000000
000000
IIS FIFO REGISTER (IISFIFO)
IIS bus interface contains two 64-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 32-
depth form, which allows the FIFO to handles data by halfword unit regardless of valid data size. Transmit and
receive FIFO access is performed through FIFO entry; the address of FENTRY is 0x44700010
Register
IISFIFO
Address
0x44700010
R/W
Description
R/W
IIS FIFO register
Reset Value
0x0
IISFIFO
FENTRY
Bit
[15:0]
Description
Transmit/Receive data for IIS
Initial State
0x0
14-7
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.