S3C24A0 Datasheet, PDF (177/487 Pages) Samsung semiconductor – APPLICATION PROCESSOR FOR 2.5G/3G MOBILE PHONES

BSW rv0.1-0417-N01
UART
S3C24A0 RISC MICROPROCESSOR
UART CONTROL REGISTER (CONTINUED)
Transmit Mode [3:2] These two bits determine which function is currently able to write Tx
00
data to the UART transmit buffer register.
00 = Disable
01 = Interrupt request or polling mode
10 = DMA0 or DMA2 request (Only for UART0),
11 = DMA1 or DMA3 request (Only for UART1)
Receive Mode [1:0] These two bits determine which function is currently able to read data
00
from UART receive buffer register.
00 = Disable
01 = Interrupt request or polling mode
10 = DMA0 or DMA2 request (Only for UART0),
11 = DMA1 or DMA3 request (Only for UART1)
Note : When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive
mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out
the rest.
11-12
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.