S3F443FX Datasheet, PDF (221/225 Pages) Samsung semiconductor – 16/32-Bit RISC Microcontroller

ELECTRICAL DATA
S3F443FX (Preliminary Spec)
EXTCLK
ADDR
nCS
t_ACS = 1
nOE
nWAIT
DATA(R)
tACC = 3
2 wait
cycle
nWAIT Sampling Points
Figure 14-8. SRAM Read Access Timing with nWAIT
During Half-Word/Word Access, except the Last Cycle
(t_COS=0, t_ACS=1, t_COH=0, t_ACC=3, external wait = 2)
EXTCLK
MCLK
(Internal Clock)
nWAIT
(1) _{Internal nWAIT}
DATA(R)
(2) _{Data Fetch Time}
NOTES:
1. External nWAIT is synchronized at the falling edge of EXTCLK.
That is, CPU recognizes the internal nWAIT as external memory wait signal.
2. Internal CPU fetches the data at the falling edge of internal clock, MCLK.
Figure 14-9. NWAIT Data Fetch Timing
14-8