S3C44B0X Datasheet, PDF (202/424 Pages) Samsung semiconductor – RISC MICROPROCESSOR

S3C44B0X RISC MICROPROCESSOR
DMA
Single Step Mode
The single step mode means that there are two DMA acknowledge cycles indicating DMA read and write cycle. The
single step mode is usually used for test or debugging because the bus mastership can be handed over to other bus
master between Read and Write. During the inactive period of nXDACK, i.e., between Read and Write cycle, the bus
controller re-evaluates the bus priority to determine the new bus mastership. Therefore, data transfer slower than that
of the hand shake mode is expected.
When the DMA request signal goes low, the bus controller indicates the bus allocation for the DMA operation by
lowering the DMA acknowledge signal if there is no higher priority bus request. During the first low level period of the
DMA acknowledge signal, there will be a DMA read cycle. After the DMA read cycle, there will be a rising of the
DMA acknowledge signal to indicate the end of the DMA read cycle. Simultaneously, the next DMA write cycle
initiates if the DMA request signal is still low at the rising edge of DMA acknowledge. But, if the DMA request signal
is already high at the rising edge of DMA acknowledge, the next DMA write cycle will be delayed until a new DMA
request signal is activated. These two cases are shown in below Figure 7-4 and Figure 7-5.
nXDREQ[1]
nXDACK[1]
nXDREQ[1]
Ready
DMA Read Cycle
DMA Write Cycle
Figure 7-4. Single Step Mode (Case 1)
nXDACK[1]
Ready
State
Idle
State
DMA Read Cycle
DMA Write Cycle
Figure 7-5. Single Step Mode (Case 2)
7-5