K7Q163664B Datasheet, PDF (2/17 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 QDR TM b4 SRAM

K7Q163664B
K7Q161864B
512Kx36 & 1Mx18 QDR^TM b4 SRAM
512Kx36-bit, 1Mx18-bit QDR^TM SRAM
FEATURES
• 1.8V/2.5V +0.1V/-0.1V Power Supply.
• I/O Supply Voltage 1.5V +0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Separate independent read and write data ports
with concurrent read and write operation.
• HSTL I/O.
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Single address bus.
• Byte writable function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7Q163664B-FC16 6.0
2.5 ns
X18
K7Q161864B-FC16 6.0
2.5 ns
FUNCTIONAL BLOCK DIAGRAM
36 (or 18) _DATA
D(Data in)
REG
17 (or 18) _ADD
ADDRESS
REG
R
W
BWX
K
K
C
C
4 (or 2)
CTRL
LOGIC
CLK
GEN
17(or 18)
72(or 36)
72(or 36)
WRITE DRIVER
512Kx36
1Mx18
MEMORY
ARRAY
72
(or 36)
72
(or 36)
SELECT OUTPUT CONTROL
144
(or 72)
36 (or 18)
Q(Data Out)
Notes: 1. Numbers in ( ) are for x18 device.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.
-2-
Mar. 2004
Rev 1.0