K7Q163664B Datasheet, PDF (10/17 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 QDR TM b4 SRAM

K7Q163664B
K7Q161864B
Overershoot Timing
VDDQ+0.7V
VDDQ+0.35V
VDDQ
20% tKHKH(MIN)
VIL
512Kx36 & 1Mx18 QDR^TM b4 SRAM
Undershoot Timing
VIH
VSS
VSS-0.35V
VSS-0.7V
20% tKHKH(MIN)
RECOMMENDED DC OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
MIN
TYP
Supply Voltage
VDD
1.7
2.5
VDDQ
1.4
1.5
Reference Voltage
VREF
0.68
0.75
Ground
VSS
0
0
MAX
2.6
1.9
0.95
0
UNIT
V
V
V
V
AC TIMING CHARACTERISTICS
Clock
PARAMETER
SYMBOL
-16
MIN
MAX
UNITS
NOTES
Clock Cycle Time(K, K, C, C)
tKHKH
6.0
Clock HIGH time (K, K, C, C)
tKHKL
2.4
Clock LOW time (K, K, C, C)
tKLKH
2.4
Clock to clock (K↑ → K↑, C↑ → C↑)
tKHKH
2.7
Clock to data clock (K↑ → C↑, K↑→ C↑) tKHCH
0.0
Output Times
ns
ns
ns
3.3
ns
2.0
ns
C, C High to Output Valid
tCHQV
2.5
ns
3
C, C High to Output hold
tCHQX
1.2
ns
3
C High to Output High-Z
tCHQZ
2.5
ns
3
C High to Output Low-Z
tCHQX1
1.2
ns
3
Setup Times
Address valid to K rising edge
tAVKH
0.7
ns
Control inputs valid to K rising edge
tIVKH
0.7
ns
2
Data-in valid to K, K rising edge
tDVKH
0.7
ns
Hold Times
K rising edge to address hold
tKHAX
0.7
v
K rising edge to control inputs hold
tKHIX
0.7
ns
K, K rising edge to data-in hold
tKHDX
0.7
ns
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W,BW0,BW1 and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 2.6V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 2.4V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 10 -
Mar. 2004
Rev 1.0