S5K433CA Datasheet, PDF (19/25 Pages) Samsung semiconductor – 1/4 Optical Size 640x480(VGA) 3.3V/2.8V VGA CMOS Image Sensor

1/4 INCH VGA CMOS IMAGE SENSOR
S5K433CA, S5K433LA
2. Analog to Digital Converter ( ADC)
The image sensor has on-chip ADC. Two-channel column parallel ADC scheme is used for separated color channel gain
and offset control.
2-1. ADC resolution
The default value of ADC resolution is 10bit and can be changed to 8bit or 9bit by control the ADC Resolution
Control Register (adcres). Lowering ADC resolution reduces the required minimum line time. When the number of
effective output bits is reduced, upper n-bits of output ports are valid and lower bits always has value of “0”.
2-2. Correlated Double Sampling ( CDS )
The analog output signal of each pixel includes some temporal random noise caused by the pixel reset action
and some fixed pattern noise by the in-pixel amplifier offset deviation. To eliminate those noise components, a
correlated double sampling(CDS) circuit is used before converting to digital. The output signal sampled twice, once
for the reset level and once for the actual signal level sampling.
2-3. Programmable Gain and Offset Control
The user can controls the gain of individual color channel by the Programmable Gain
Control Registers (pgcr, pgcg1, pgcg2, pgcb) and offset by Offset Control Registers (offsr,
offsg1, offsg2, offsb). If the Color Channel Separation Mode is disabled (ccsm=0), pgcg1
and offsg1 change the gains and offsets for all channels. As increasing the gain control
register, the ADC conversion input range decreases and the gain increased as following
equation:
R G1 R G1
G2 B G2 B
R G1 R G1
G2 B G2 B
Channel Gain = 128 / (128 – Programmable Gain Control Register Value[6:0])
10
9
8
7
6
5
4
3
2
1
0
16 32 48 64 80 96 112 128
Programmable Gain Control
45
40
35
30
25
20
15
10
5
0
0
16 32 48 64 80 96 112 128
Programmable Gain Control
Figure 6. Relative Channel Gain
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