K8S5615ETC Datasheet, PDF (19/65 Pages) Samsung semiconductor – 256Mb C-die NOR Flash

K8S5615ETC
Rev. 1.0
datasheet ^{NOR FLASH MEMORY}
The abort condition is indicated by DQ1 = 1, DQ7 = DATA (for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-to-Buffer-Abort
Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of Write-to-Buffer-Abort Reset command
sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode.
And from the third cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Programming features in Unlock Bypass
mode. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the DQ7 and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1."
9.15 Accelerated Write Buffer Programming
The device provides accelerated Write Buffer Program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory
is possible. When VID is asserted on the Vpp input, the device temporarily unprotects any protected blocks, and uses the higher voltage on the input to
reduce the time required for program operations. In accelerated Write Buffer Program mode, the system must enter "Write to Buffer" and "Program Buffer
to Flash" command sequence to be same as them of normal Write Buffer Programming. Note that the third cycle of "Write to Buffer Abort Reset" com-
mand sequence is required in an accelerated mode.
Note that Read While Accelerated Write Buffer Program and Program suspend mode are not guaranteed.
• Program/Erase cycling must be limited below 100cycles for optimum performance.
• Ambient temperature requirements : T_A = 30°C±10°C
9.16 Chip Erase
To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the
command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip
erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The
automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns
to the read mode.
9.17 Block Erase
To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the
command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two
more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior
to erasing it. The block address is latched on the rising edge of AVD , while the Block Erase command is latched on the rising edge of WE. Multiple blocks
can be erased sequentially by writing the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block
Erase command (30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is
needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase com-
mand writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us
"time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of
"time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After
the 50us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and
command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend com-
mand during Block Erase operation.
The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device automatically enters the
Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. By
removing VID returns the device to normal operation mode.
9.18 Unlock Bypass
The K8S(54/55/56/57)15E provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase, chip erase, write
to buffer and write to buffer abort reset operation.. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass
command sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four bus cycles, the unlock
bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command
sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H).
Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program com-
mand sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data.
This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command
sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase com-
mand(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command
sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles.
The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode.
To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass mode.
Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just remove the
asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always connected with VIH, VIL or VID.).
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