K4T51043Q Datasheet, PDF (19/28 Pages) Samsung semiconductor – 512Mb B-die DDR2 SDRAM

512Mb B-die DDR2 SDRAM
DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read command
Exit active power down to read command
Exit active power down to read command
(slow exit, lower power)
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
DDR2-533
min
max
-500
+500
-450
+450
0.45
0.55
0.45
0.55
min(tCL, tCH)
x
3750
8000
225
x
100
x
0.6
x
0.35
x
x
tAC max
tAC min
tAC max
2* tACmin tAC max
x
300
x
400
tHP - tQHS
x
-0.25
0.25
0.35
x
0.35
x
0.2
x
0.2
x
2
x
0.4
0.6
0.35
x
375
x
250
x
0.9
1.1
0.4
0.6
7.5
x
10
x
37.5
50
2
15
x
WR+tRP
x
7.5
x
7.5
tRFC + 10
200
2
x
2
x
DDR2-400
min
max
-600
+600
-500
+500
0.45
0.55
0.45
0.55
min(tCL, tCH)
x
5000
8000
275
x
150
x
0.6
x
0.35
x
x
tAC max
tAC min
tAC max
2* tACmin
tAC max
x
350
x
450
tHP - tQHS
x
-0.25
0.25
0.35
x
0.35
x
0.2
x
0.2
x
2
x
0.4
0.6
0.35
x
475
x
350
x
0.9
1.1
0.4
0.6
7.5
x
10
x
37.5
50
2
15
x
WR+tRP
x
10
x
7.5
tRFC + 10
200
2
x
2
x
6 - AL
6 - AL
Units
Notes
ps
ps
tCK
tCK
ps
20,21
ps
24
ps
15,16,17,20
ps
15,16,17,21
tCK
tCK
ps
ps
27
ps
27
ps
22
ps
21
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
19
tCK
ps
14,16,18,23
ps
14,16,18,22
tCK
28
tCK
28
ns
12
ns
12
ns
ns
tCK
ns
tCK
23
ns
33
ns
11
ns
tCK
tCK
tCK
9
tCK
9, 10
Page 19 of 28
Rev. 1.5 July 2005