K7R161882B Datasheet, PDF (18/19 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 & 2Mx9 QDRTM II b2 SRAM

K7R163682B
K7R161882B
K7R160982B
512Kx36 & 1Mx18 & 2Mx9 QDR^TM II b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
Power Supply Voltage
VDD
1.7
Input High Level
VIH
1.3
Input Low Level
VIL
-0.3
Output High Voltage(IOH=-2mA)
VOH
1.4
Output Low Voltage(IOL=2mA)
VOL
VSS
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
Typ
Max
Unit
1.8
1.9
V
-
VDD+0.3
V
-
0.5
V
-
VDD
V
-
0.4
V
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Input Rise/Fall Time
Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
JTAG AC Characteristics
Parameter
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
JTAG TIMING DIAGRAM
Symbol
VIH/VIL
TR/TF
Symbol
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
Min
1.8/0.0
1.0/1.0
0.9
Min
Max
50
-
20
-
20
-
5
-
5
-
5
-
5
-
5
-
5
-
0
10
Unit
V
ns
V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Note
1
Note
TCK
TMS
TDI
PI
(SRAM)
TDO
tCHCH
tMVCH
tDVCH
tCHMX
tCHCL
tCHDX
tSVCH
tCHSX
tCLQV
- 18 -
tCLCH
June. 2004
Rev 3.0