KS0074 Datasheet, PDF (15/70 Pages) Samsung semiconductor – 34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

KS0074
34COM/80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Timing Generation Circuit
Timing generation circuit generates clock signals for the internal operations.
Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0~DB6 ports.
Cursor/Blink Control Circuit
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
LCD Driver Circuit
LCD Driver circuit has 34 common and 80 segment signals for LCD driving.
Data from SEGRAM/CGRAM/CGROM is transferred to 80-bit segment latch serially, which is then stored to
80-bit shift latch. When each common is selected by 34-bit common register, segment data also
output through segment driver from 80-bit segment latch.
In 1-line display mode, COM0  COM17 have 1/17 duty, and in 2-line or 4-line mode,
COM0  COM33 have 1/33 duty ratio.