K7D163674B Datasheet, PDF (15/16 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 SRAM

K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input High Level
Input Low Level
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
Symbol
Min
Typ
Max
Unit
VDD
1.7
2.5
2.6
V
VIH
0.7*VDD
-
VDD+0.3
V
VIL
-0.3
-
0.3*VDD
V
VOH
0.75*VDD
-
VDD
V
VOL
VSS
-
0.25*VDD
V
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
Min
Unit
Input High/Low Level
VIH/VIL
VDD/0.0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
Input and Output Timing Reference Level
VDD/2
V
NOTE : 1. See SRAM AC test output load on page 5.
JTAG AC Characteristics
Parameter
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
Clock Low to Output Valid
Symbol
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tCLQV
Min
50
20
20
5
5
5
5
0
Max
-
-
-
-
-
-
-
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
JTAG TIMING DIAGRAM
Note
Note
1
Note
TCK
TMS
TDI
TDO
tCHCH
tMVCH
tDVCH
tCHCL
tCHMX
tCHDX
tCLQV
tCLCH
- 15
Rev 1.1
Jan. 2005