S6B0108 Datasheet, PDF (14/23 Pages) Samsung semiconductor – 64 CH SEGMENT DRIVER FOR DOT MATRIX LCD

S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
OPERATING PRINCIPLES AND METHODS
I/O BUFFER
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active
mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB
and ADC can operate regardless CS1B-CS3.
INPUT REGISTER
Input register is provided to interface with MPU which is different operating frequency. Input register stores the
data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS
select the input register. The data from MPU is written into input register. Then Writing it into display RAM. Data
latched for falling of the E signal and write automatically into the display data RAM by internal operation.
OUTPUT REGISTER
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active
mode and R/W and RS = H, stored data in display data RAM is latched in output register. When CS1B to CS3 is
in active mode and R/W = H, RS = L, status data (busy check) can read out. To read the contents of display data
RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output
register. In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it
needs dummy read. But status read is not needed dummy read.
RS
R/W
Function
L
Instruction
L
H
Status read (busy check)
L
Data write (from input register to display data RAM)
H
H
Data read (from display data RAM to output register)
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