K7A403200M Datasheet, PDF (14/15 Pages) Samsung semiconductor – 128Kx32-Bit Synchronous Pipelined Burst SRAM

K7A403200M
128Kx32 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx32 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
Data
Address
A[0:17]
A[17] A[0:16]
I/O[0:63]
A[17] A[0:16]
CLK
64-Bits
Microprocessor
ADS
Address
CLK
Cache
Controller
Address Data
CS2
CS2
CLK
ADSC
WEx
OE
128Kx32
SPB
SRAM
(Bank 0)
CS1
ADV ADSP
Address Data
CS2
CS2
CLK
ADSC
WEx
OE
128Kx32
SPB
SRAM
(Bank 1)
CS1
ADV ADSP
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
tSS
tSH
ADDRESS ^A1
[0:n]
tWS
tWH
WRITE
tAS
tAH
A2
CS1
An+1
ADV
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
tADVS
tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
OE
Data Out
(Bank 0)
tOE
tLZOE
Q1-1
Data Out
(Bank 1)
*Notes :
n = 14 32K depth
15 64K depth
16 128K depth
17 256K depth
Q1-2
Q1-3
tHZC
Q1-4
tCD
tLZC
Q2-1 Q2-2 Q2-3 Q2-4
Don′t Care Undefined
- 14 -
February 1999
Rev 5.0