M368L3223ETN Datasheet, PDF (13/22 Pages) Samsung semiconductor – DDR SDRAM Unbuffered Module

256MB, 512MB Unbuffered DIMM
DDR SDRAM
AC Timming Parameters & Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
CL=2.0
CL=2.5
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate Matching Ratio(rise to fall)
B3
AA
A2
B0
Symbol ^{(DDR333@CL=2.5) (DDR266@CL=2.0 (DDR266@CL=2.0) (DDR266@CL=2.5)} Unit
Min
Max
Min
Max
Min
Max
tRC
60
60
65
65
ns
tRFC
72
75
75
75
ns
tRAS
42
70K
45
120K
45
120K
45
120K ns
tRCD
18
15
20
20
ns
tRP
18
15
20
20
ns
tRRD
12
15
15
15
ns
tWR
15
15
15
15
ns
tWTR
1
1
1
1
tCK
tCCD
1
1
1
1
tCK
7.5
12
7.5
12
7.5
12
10
12
ns
tCK
6
12
7.5
12
7.5
12
7.5
12
ns
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55 tCK
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55 tCK
tDQSCK -0.6
+0.6
-0.75
+0.75
-0.75
+0.75
-0.75
+0.75 ns
tAC
-0.7
+0.7
-0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns
tDQSQ
-
0.45
-
0.5
-
0.5
-
0.5
ns
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25 tCK
tWPRES
0
0
0
0
ns
tWPRE 0.25
0.25
0.25
0.25
tCK
tDSS
0.2
0.2
0.2
0.2
tCK
tDSH
0.2
0.2
0.2
0.2
tCK
tDQSH
0.35
0.35
0.35
0.35
tCK
tDQSL
0.35
0.35
0.35
0.35
tCK
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
tIS
0.75
0.9
0.9
0.9
ns
tIH
0.75
0.9
0.9
0.9
ns
tIS
0.8
1.0
1.0
1.0
ns
tIH
0.8
1.0
1.0
1.0
ns
tHZ
-0.7
+0.7
-0.75
+0.75 -0.75
+0.75 -0.75
+0.75 ns
tLZ
-0.7
+0.7
-0.75
+0.75 -0.75
+0.75 -0.75
+0.75 ns
tSL(I)
0.5
0.5
0.5
0.5
V/ns
tSL(IO)
0.5
0.5
0.5
0.5
V/ns
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
1.0
4.5 V/ns
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
0.67
1.5
Note
12
3
i,5.7~9
i,5.7~9
i, 6~9
i, 6~9
1
1
Rev. 1.1 August. 2003