K7R643684M Datasheet, PDF (13/18 Pages) Samsung semiconductor – 2Mx36 & 4Mx18 QDRTM II b4 SRAM

K7R643684M
K7R641884M
Preliminary
2Mx36 & 4Mx18 QDR^TM II b4 SRAM
TIMING WAVE FORMS OF READ AND NOP
READ
tKHKH
tKLKH
K
READ
tKHKL
tKHKH
K
tAVKH tKHAX
NOP
NOP
SA
A1
tIVKH tKHIX
R
Q
(Data Out)
C
C
tKHKH
tKLKH
tKHKL
CQ
CQ
A2
tCHQX1
tKHCH
Q1-1 Q1-2
tCHQV tCHQX
Q1-3
Q1-4
Q2-1
Q2-2
Q2-3
Q2-4
tKHKH
tCHQV
tCQHQV
tCHCQV
tCHCQX
tCQHQX
tCHCQV
tCHCQX
tCHQZ
Don′t Care Undefined
Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
TIMING WAVE FORMS OF WRITE AND NOP
WRITE
tKHKH
tKLKH
K
WRITE
tKHKL
tKHKH
K
tAVKH tKHAX
SA
A1
tIVKH tKHIX
W
A2
tKHIX
NOP
NOP
D(Data In)
D1-1 D1-2 D1-3 D1-4 D2-1 D2-2 D2-3 D2-4
tDVKH
tKHDX
Don′t Care
Note: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+0.
2. BWx assumed active.
Undefined
- 13 -
Oct. 2004
Rev 0.5