K7D323674A Datasheet, PDF (13/19 Pages) Samsung semiconductor – 32Mb A-die DDR SRAM Specification

K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
AC TEST OUTPUT LOAD
25Ω
DQ
50Ω
5pF
0.75V
50Ω
5pF
50Ω
50Ω
0.75V
0.75V
AC TIMING CHARACTERISTICS
PARAMETER
SYMBOL
-40
MIN
MAX
Clock
Clock Cycle Time
tKHKH
2.50
5.00
Clock High Pulse Width
tKHKL
1.15
Clock Low Pulse Width
tKLKH
1.15
Setup Times
Address Setup Time
tAVKH
0.30
Control(B1,B2,B3) Setup Time
tBVKH
0.30
Data Setup Time
tDVKX
0.20
Hold Times
Address Hold Time
tKHAX
0.30
Control(B1,B2,B3) Hold Time
tKHBX
0.30
Data Hold Time
tKXDX
0.20
Output Times
Echo Clock High Pulse Width
tCHCL
tKHKL-0.1 tKHKL+0.1
Echo Clock Low Pulse Width
tCLCH
tKLKH-0.1 tKLKH+0.1
Clock Crossing to Echo Clock
tCXCH
1.0
2.5
Clock Crossing to Echo Clock
tCXCL
1.0
2.5
Echo Clock High to Output Vaild tCHQV
0.20
Echo Clock Low to Output Valid
tCLQV
0.20
Echo Clock High to Output Hold tCHQX
-0.20
Echo Clock Low to Output Hold
tCLQX
-0.20
Echo Clock High to Output High-Z tCHQZ
0.20
Echo Clock High to Output Low-Z tCHLZ
-0.20
-37
MIN
MAX
2.67
6.00
1.25
1.25
0.33
0.33
0.25
0.33
0.33
0.25
tKHKL-0.1
tKLKH-0.1
1.0
1.0
-0.20
-0.20
-0.20
tKHKL+0.1
tKLKH+0.1
2.5
2.5
0.20
0.20
0.20
-33
MIN
MAX
UNITS NOTES
3.00
6.00
ns
1
1.40
ns
1.40
ns
0.35
ns
0.35
ns
0.30
ns
2
0.35
ns
0.35
ns
0.30
ns
2
tKHKL-0.1 tKHKL+0.1
ns
2
tKLKH-0.1 tKLKH+0.1
ns
2
1.0
2.5
ns
3
1.0
2.5
ns
3
0.20
ns
0.20
ns
-0.20
ns
-0.20
ns
0.20
ns
-0.20
ns
Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification.
2. This parameter is guaranteed by design, and may not be tested at values shown in the table.
3. This parameter refers to CQ and CQ rising and falling edges.
4. This parameter is only for 32Mb density
5. K and K Clocks must be used differencitally to meet AC timing specifications.
- 13
Rev 1.4
Oct. 2005