S6A0032 Datasheet, PDF (11/39 Pages) Samsung semiconductor – 16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.5
S6A0032
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
S6A0032 has two kinds of interface type with MPU: 4-bit bus or 8-bit bus. 4-bit bus and 8-bit bus is selected by the
DL bit in the instruction register, and 6800-series MPU or 8080-series MPU is selected by MI pin.
MI
6800
series (H)
8080
series (L)
Table 4. Various Kinds of MPU Interface according to MI and DL Bit
DL
CSB
RS
RW_WR
E_RD
DB0 to DB3
8-bit (H)
CSB
RS
R/W
E
DB0 to DB3
4-bit (L)
CSB
RS
R/W
E
-
8-bit (H)
CSB
RS
WR
RD
DB0 to DB3
4-bit (L)
CSB
RS
WR
RD
-
NOTE: "-" - Dont’ care ("High", "Low" or Open)
(H): fixed "High" (VDD)
(L): fixed "Low" (VSS)
DB4 to DB7
DB4 to DB7
DB4 to DB7
DB4 to DB7
DB4 to DB7
MI: "High" = 6800-series MPU, "Low" = 8080-series MPU
DL: "High" = 8-bit mode, "Low" = 4-bit mode
CSB: "High" = chip is not selected, "Low" = chip is selected
RS: "High" = data register, "Low" = instruction register
RW_WR: read / write indicating signal in 6800 mode, active high signal for writing command in 8080 mode.
E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode,
low enable signal for reading command in 8080 mode.
Parallel Interface
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM. Target RAM is
selected by RAM address set instruction. The Instruction register (IR) is used only to store instruction code
transferred from MPU. To select DR or IR register, RS input pin is used.
During reading operation, 8-bit output data register (OR) is used. The output data register (OR) is used as temporary
data storage place for being read from DDRAM / CGRAM. Destination RAM is selected by RAM address set
instruction. After RAM address set, the first reading in the 8-bit bus mode (first and second reading in the 4-bit bus
mode) is a dummy cycle (figure 3, 4, 5, 6). The valid data comes from the second reading in the 8-bit bus mode (from
the 3rd reading in 4-bit bus mode). The dummy cycle makes the address counter (AC) indicate the correct address.
So it is recommended to set address before writing. The instruction read operation is supported for indicating
internal operation is being processed (Busy Flag).
In the 4-bit bus mode, it is needed to transfer 4-bit data (through DB4 to DB7) by two times. The high order bits (for
8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3) in read and write
transaction. The DB0 to DB3 pins are floated in this 4-bit bus mode.
After RESETB operation, S6A0032 considers the first 4-bit data from MPU as the high order bits in the 4-bit bus
mode.
7