K4X56163PG Datasheet, PDF (11/23 Pages) Samsung semiconductor – 16M x16 Mobile-DDR SDRAM

K4X56163PG - L(F)E/G
Mobile-DDR SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Symbol
Test Condition
DDR266 DDR222 Unit
Operating Current
(One Bank Active)
IDD0 ^{tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid commands;}
50
address inputs are SWITCHING; data bus inputs are STABLE
45
mA
Precharge Standby Current in
all banks idle, CKE is LOW; CS is HIGH, tCK = t CKmin ; address and control inputs are
IDD2P _{SWITCHING; data bus inputs are STABLE}
0.3
power-down mode
mA
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control
IDD2PS _{inputs are SWITCHING; data bus inputs are STABLE}
0.3
Precharge Standby Current
IDD2N ^{all banks idle, CKE is HIGH; CS is HIGH, tCK = t CKmin ;address and control inputs are}
12
SWITCHING; data bus inputs are STABLE
in non power-down mode
IDD2NS ^{all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control}
8
inputs are SWITCHING; data bus inputs are STABLE
10
mA
6
IDD3P ^{one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin ;address and control inputs are}
5
Active Standby Current
in power-down mode
SWITCHING; data bus inputs are STABLE
mA
IDD3PS ^{one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;address and control}
2
inputs are SWITCHING; data bus inputs are STABLE
Active Standby Current
IDD3N ^{one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin ;address and control inputs}
25
are SWITCHING; data bus inputs are STABLE
in non power-down mode
(One Bank Active)
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
IDD3NS address and control inputs are SWITCHING; data bus inputs are STABLE
20
20
mA
15
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Deep Power Down Current
IDD4R ^{one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts; I OUT = 0 mA}
100
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W ^{one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;address inputs are}
90
SWITCHING; 50% data change each burst transfer
85
mA
80
IDD5 ^{tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;address and control inputs}
100
are SWITCHING; data bus inputs are STABLE
CKE is LOW; tCK = tCKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
TCSR Range
45*¹
Full Array
200
-E
1/2 Array
160
IDD6
1/4 Array
140
Full Array
150
90
mA
85
°C
450
300
250
uA
300
-G
1/2 Array
135
250
1/4 Array
130
225
IDD8*² Address and control inputs are STABLE; data bus inputs are STABLE
10
uA
Note :
1. It has +/- 5°C tolerance.
2. DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
3. IDD specifications are tested after the device is properly intialized.
4. Input slew rate is 1V/ns.
5. Definitions for IDD: LOW is defined as V IN ≤ 0.1 * V DDQ ;
HIGH is defined as V IN ≥ 0.9 * V DDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
January 2006