K4S280432F Datasheet, PDF (10/14 Pages) Samsung semiconductor – 128Mb F-die SDRAM Specification

SDRAM 128Mb F-die (x4, x8, x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Output
870Ω
3.3V
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Unit
V
V
ns
V
Z0 = 50Ω
Vtt = 1.4V
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
CAS latency=3
CAS latency=2
Version
60 (x16 only)
75
12
15
18
20
18
20
42
45
100
60
65
2
2 CLK + tRP
1
1
1
2
-
1
Unit
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Note
1
1
1
1
1
2,5
5
2
2
3
4
Rev. 1.2 May 2004