SA2007H Datasheet, PDF(6/10 Page) Sames – Single Phase Bidirectional Dual Element Power/Energy Metering IC with Pulse Output

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SA2007H Datasheet, PDF (6/10 Pages) Sames – Single Phase Bidirectional Dual Element Power/Energy Metering IC with Pulse Output

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SA2007H

Positive energy flow, when voltage sense and both current

sense input are in phase, is indicated on pin D1 or D2 as a logic

Figure 5 shows the behavior of D1 and D2, when energy

reversal takes place. The time period for the direction signal to

change state, tDIR, is the time it takes for the internal integrator

to count (down) from its present value to zero. Thus the energy

consumption rate determines the speed of change on the

direction outputs.

D1, D2

DR-01283

t DIR

Figure 5: Measured energy direction on D1 or D2

Mains zero crossing indication (FMO)

The square wave signal of FMO indicates the polarity of the

mains voltage. Due to comparator offsets, the FMO low to high

transition can occur within a range as shown in figure 6. The

time between successive low to high transitions will be equal to

the mains voltage period.

sames

Interrupt (INT)

While the SA2007H is operating in latched mode (see Output

mode description) an interrupt is generated with the falling

edge of the pulse outputs P1 and P2 (see figure 7). INT is

cleared with a logic 1 on the RP input.

OUTPUT SIGNALS IN LATCHED MODE

Latched mode is selected by setting the OMODE input to logic

1. This mode is used with a micro controller to ensure that any

simultaneous pulses on P1 and P2 are not missed. The

functionality of the latched mode is shown in figure 7.

An interrupt is generated with a falling edge on any of the pulse

output signals P1 and P2. The micro controller needs to scan

the status of the pulse outputs as well as the direction signals

D1 and D2 during its interrupt service routine. The micro

controller clears the interrupt by setting the RP input to a logic

1. The pulse outputs P1 and P2 are cleared along with the

interrupt. Note that energy pulses are inhibited when the

interrupt output is set (during latched mode).

FMO

INT

dr-01621

Figure 7: Output signals in latched mode

FMO

t MAINS

DR-01284

Figure 6: Mains zero crossing on FMO

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PRELIMINARY

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