BU9883FV-W_1 Datasheet, PDF (9/19 Pages) Rohm – I2C BUS3Ports for HDMI Port Serial EEPROM

BU9883FV-W
Technical Note
○DEVICE ADDRESSING
・Following a START condition, the master output the device address of the slave to be accessed.
The most significant four bits of the slave address are the “device type indentifier,” for this device, this is fixed as “1010.”
The next three bit specify a particular device. For PORT0 access, that are set “0”, “P1”, “P0”, for PORT 1～3 access, that
must be set “000”.
The last bit of the stream determines the operation to be performed.
When set to “1” a read operation is selected ; when set to “0,” a write operation is selected.
R/W set to “0” ･ ･ ･ ･ ･ ･ ･ ･ WRITE
R/W set to “1” ･ ･ ･ ･ ･ ･ ･ ･ READ
○ACKNOWLEDGE
・Acknowledge is a software convention used to indicate successful data transfers.The master or the slave will release the
bus after transmitting eight bits.During the ninth clock cycle, the receiver will pull the SDA line LOW to Acknowledgethat
the eight bits of data has been received.
・This device will respond with an Acknowledge after recognition of a START condition and its slave address.If both the
device and a write operation have been selected, this device will respond with an Acknowledge, after the receipt of each
subsequent 8-bit word.
・In the READ mode, this device will transmit eight bit of data, release the SDA line, and monitor the line for an
Acknowledge.
・If an Acknowledge is detected, and no STOP condition is generated by the master, this device will continue to transmit
the data.
・If an Acknowledge is not detected, this device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
・This device dosen't return Acknouwedge in internal write cycle.
START CONDITION
(START BIT)
SCL
（Fromμ-COM）
1
8
9
SDA
（μ-COM
OUTPUT DATA)
SDA
（IC OUTPUT DATA）
Acknowledge Signal
(ACK Signal)
Fig.41 ACKNOWLEDGE RESPONSE FROM RECEIVER
●PORT0 access commands
○For PORT0 access, WPB terminal must be set to “HIGH”.
S
W
T
R
A
I
R
SLAVE
T
T
ADDRESS
E
1st WORD
ADDRESS(n)
DATA(n)
SDA
LINE
1 0 1 0 0 P1 P0
WA7
WA0 D7
WPB
RA
/C
WK
S
T
O
P
D0
A
C
K
Fig.42 BYTE WRITE CYCLE TIMING (PORT0)
○This write commands operate EEPROM write sequence at address which is appointed by P1, P0. When the master
generates a STOP condition, this device begins the internal write cycle to the nonvolatile array.
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2009.04 - Rev.B