BU9883FV-W_1 Datasheet, PDF (10/19 Pages) Rohm – I2C BUS3Ports for HDMI Port Serial EEPROM

BU9883FV-W
Technical Note
SDA
LINE
S
W
T
R
A
I
R
SLAVE
T
T
ADDRESS
E
1st WORD
ADDRESS(n)
1 0 1 0 0 P1 P0
WA7
WA0 D7
RA
A
/C
C
WK
K
WPB
DATA(n)
D0
A
C
K
S
T
DATA(n+7)
O
P
D0
A
C
K
Fig.43 PAGE WRITE CYCLE TIMING (PORT0)
○This device is capable of eight byte page write operation.
○After the receipt of each word, the three low order address bits are internally incremented by one. The most
significant address bits (WA7～WA3) remain constant, if the master transmits more than 8 words.
○The relationship of P1, P0 inputs and access BANK is described as follows.
P1 P0
0
0
0
1
1
0
1
1
BANK
No opearation
BANK1
BANK2
BANK3
○Don't set P1, P0=0, 0. If P1, P0 are set to 0, there is no target bank, so this device doesn't return cknowlege.
○WPB terminal must be set to “HIGH” during Byte Write cycle, and Page Write cycle, and internal Write cycles. If WPB is
set to “LOW” in above condition, programing doesn't work, and during internal Write cycle, WPB terminal set to “LOW”,
this device terminate programing, and the data in programing address is not stored correctly.
SDA
LINE
S
W
T
R
A
I
R
SLAVE
T
T
ADDRESS
E
1st WORD
ADDRESS(n)
S
T
R
A
R
T
SLAVE
ADDRESS
E
A
D
DATA(n)
1 0 1 0 0 P1 P0
WA7
WA0
1 0 1 0 0 P1 P0
D7
S
T
O
P
D0
RA
A
RA
A
/C
C
/C
C
WK
K
WK
K
WPB
Fig.44 RANDOM READ CYCLE TIMING（PORT0）
○Random read operation allows the master to access any memory location which is appointed by P1, P0 bit.
This operation involves a two-step process.
First, the master issue a write command which includes the start condition and the slave address field (with R/W set to “0”)
followed by the address of the word be read.
This procedure sets the internal address counter of this device to the desired address. After the word address
acknowledge is received by the master, the master immediately reissues a start condition followed by the slave address
field with R/W the set to “1.” This device will respond with an acknowledge and then transmit the 8-data bits stored at the
addressed location.
If the master does not acknowledge the transmission but does generate the stop condition, at this point this device
discontinues transmission.
S
T
R
S
A
SLAVE
E
T
R
ADDRESS
A
O
T
D
DATA
P
SDA
LINE
1 0 1 0 0 P1 _P0
D7
RA
/C
WK
D0
A
C
K
WPB
Fig.45 CURRENT READ CYCLE TIMING（PORT0）
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© 2009 ROHM Co., Ltd. All rights reserved.
10/18
2009.04 - Rev.B