BD9486F Datasheet, PDF (9/37 Pages) Rohm – 1ch Boost up type White LED Driver for large LCD

BD9486F
Datasheet
●2.5 Pin Description
○Pin 1: REG50
This is the 5.0V(typ.) output pin. Available current is 5mA (min).
And this terminal is also used as timer for discharging DCDC output capacitor.
Please refer to section“3.2.2 Shutdown Method and REG50 Capacitance Setting”, for detailed explanation.
○Pin 2: STB
This is the ON/OFF setting terminal of the IC. Input reset-signal to this terminal to reset IC from latch-off.
At startup, internal bias starts at high level, and then PWM DCDC boost starts after PWM rise edge inputs.
Note: IC status (IC ON/OFF) transits depending on the voltage inputted to STB terminal. Avoid the use of intermediate
level (from 0.8V to 2.0V).
In order to discharge output voltage while STB=L and REG50UVLO=H, DIMOUT can assert High, depending on PWM
logic. About discharge behavior at end, please refer to section “3.5.3 Timing Chart” or section “3.2.2 Shutdown Method
and REG50 Capacitance Setting”.
○Pin 3: OVP
The OVP terminal is the input for over-voltage protection. If OVP is more than 3.0V(typ), the over-voltage protection
(OVP) will work. At the moment of these detections, it sets GATE=L, DIMOUT=L and starts to count up the abnormal
interval. If OVP detection continued to count four GATE clocks, IC reaches latch off. (Please refer to “3.5.5 Timing Chart”)
The OVP pin is high impedance, because the internal resistance is not connected to a certain bias.
Even if OVP function is not used, pin bias is still required because the open connection of this pin is not a fixed potential.
The setting example is separately described in the section ”3.2.7 OVP Setting”.
As PWM=L interval, IC operates to keep the OVP pin voltage therefore the output voltage. Please refer the section “TBD
the Retaining Function of The Output Voltage”.
○Pin 4: UVLO
Under Voltage Lock Out pin is the input voltage of the power stage. , IC starts the boost operation if UVLO is more than
3.0V(typ) and stops if lower than 2.7V(typ).
The UVLO pin is high impedance, because the internal resistance is not connected to a certain bias.
Even if UVLO function is not used, pin bias is still required because the open connection of this pin is not a fixed
potential.
The setting example is separately described in the section ”3.2.6 UVLO Setting”
○Pin 5: SS
This is the pin which sets the soft start interval of DC/DC converter. It performs the constant current charge of 3.0 μA to
external capacitance Css. The switching duty of GATE output will be limited during 0V to 3.7V of the SS voltage.
So the soft start interval Tss can be expressed as follows
Tss = 1.23*10⁶*Css
Css: the external capacitance of the SS pin.
The logic of SS pin asserts low is defined as the latch-off state or PWM is not input high level after STB reset release.
When SS capacitance is under 1nF, take note if the in-rush current during startup is too large, or if over boost detection
(FBMAXI) mask timing is too short.
Please refer to soft start behavior in the section “3.5.4 Timing Chart ”.
○Pin 6: PWM
This is the PWM dimming signal input terminal. The high / low level of PWM pins are the following.
State
PWM=H
PWM=L
PWM input voltage
PWM=1.5V to 18.0V
PWM=‐0.3V to 0.8V
○Pin 7: CP
Timer pin for counting the abnormal state of the over boost protection (FBMAX). If the abnormal state is detected, the CP
pin starts charging the external capacitance by 3μA. As the CP voltage reaches 3.0V, IC will be latched off. (GATE=L,
DIMOUT=L).
Please refer to section“3.2.8 Interval Until Latch Off Setting”, for detailed explanation.
○Pin 8: ADIM
This is the input pin for analog dimming signal. The ISENSE feedback point is set as 1/3 of this pin bias. If more than 3.0V
is input, ISENSE feedback voltage is clamped to limit to flow LED large current. In this condition, the input current is
caused. Please refer to <ISENSE> terminal explanation.
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TSZ02201-0F1F0C100240-1-2
13.Feb.2014 Rev.004