BD9483F Datasheet, PDF (9/32 Pages) Rohm – White LED Driver for large LCD Panels (DCDC Converter type)

BD9483F,FV
Datasheet
●3.1 Pin Function
VCC （1 PIN）
Power supply pin of IC. Input range is from 11V to 35.0V.
The operation starts more than 7.0V(typ.) and shuts down less than 6.7V(typ.) by VCCUVLO.
In the lower VCC than 7.6V(typ.), IC stops switching by REG90UVLO, which detect the lower voltage of VCC earlier than
VCCUVLO.
STB （2 PIN）
STB can be used to perform the reset of latch off or soft start. The power control of REG90 is depend on STB pin and the
VCCUVLO.
Regarding of the sequence of turning on, after the positive edge of PWM is input, BD9483F,FV starts the boost operation
and the soft start.
The input voltage of STB pin toggles the IC state(IC ON/OFF). Please avoid the use of the intermediate level (from 0.8V
to 2.0V).
CS1 （3 PIN）, CS2 (23 PIN)
The CS pin has two functions.
1. DC / DC current mode Feedback terminal
VIN
The inductor current is converted to the CS pin voltage by the sense resistor R_CS
and this CS pin voltage controls the gate duty.
2. Inductor current limit (OCP) terminal
The CS terminal also has an over current protection (OCP), if it voltage is more
than 0.4V, the switching operation will be stopped compulsorily. And the next
GATE
boost pulse will be restart in normal frequency.
If the capacitance Cs in the right Figure is increased to a micro orders, please be
careful that the limited value of NMOS drain current Id is much than the simple
calculation. Because the current Id flow not only Rcs but also Cs, as the CS pin
CS
Cs
Rcs
voltage move according to Id.
GND
Figure 13.
Both of above functions are enable after 300ns (typ.) when GATE pin asserts
high, because the leading Edge Blanking function is included into this IC to prevent the noise affection. Please refer to
the section “●3.5.1 how to set OCP / the calculation method for the current rating of DCDC parts”, for detail explanation.
GATE1 （4 PIN）, GATE2 (22 PIN)
This is the output terminal for driving the gate of the boost MOSFET. The high level is REG90 of IC. Frequency can be
set by the resistor connected to RT. Please refer to the <RT> pin description for the frequency setting.
In the condition of approximately VCC<9.8V, the high level of the GATE pin is about VCC-0.8V, which lower than 9.0V.
The phase lag of GATE1 and GATE2 is shown in Figure below. This Figure illustrates the waveform as both GATE pin
output the maximum duty. The inrush current of the VIN terminal can be suppressed because each channel turns on
alternately.
GND1 （5 PIN）, GND2 (21 PIN)
GND pin of IC. GND1 is the ground pin of channel 1.
Figure 14.
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28.Nov.2013 Rev.003